1. Field of the Invention
The invention relates to a semiconductor device having a plurality of wiring layers and also to a method of fabricating the same, and more particularly to an improvement in electrical connection between upper and lower wiring layers.
2. Description of the Related Art
With recent enhancement in integration of a semiconductor device, a width of a wiring layer and a diameter of a via-hole for electrically connecting upper and lower wiring layers to each other are made smaller and smaller. However, if a diameter of a via-hole is reduced down to half-micron level, it would be quite difficult or almost impossible to sufficiently fill the via-hole with aluminum by sputtering. As a result, it would be necessary to form a contact plug by filling a via-hole with refractory metal such as tungsten (W) by chemical vapor deposition (CVD).
FIG. 1 is a cross-sectional view of a conventional semiconductor device having a contact plug. Silicon dioxide films 2 formed at a surface of a p-type silicon substrate 1 for element isolation defines element formation regions therebetween. After a MOS transistor including a gate electrode 4 formed on the silicon substrate 1 with a gate oxide film 3 sandwiched therebetween, source and drain regions 5-1 and 5-2 formed at a surface of the silicon substrate 1 has been formed in one of the element formation regions, an interlayer insulating film 6 is deposited on the silicon substrate 1.
Then, contact holes 7-1 and 7-2 are formed throughout the interlayer insulating film 6. The contact holes 7-1 and 7-2 reach the source and drain regions 5-1 and 5-2, respectively. Then, contact plugs 8-1 and 8-2 are formed by filling the contact holes 7-1 and 7-2 with tungsten, respectively. As suggested in Japanese Unexamined Patent Publication No. 60-115245, the contact plugs 8-1 and 8-2 may be formed by depositing tungsten in the contact holes 7-1 and 7-2 by selective CVD, or by depositing tungsten all over the interlayer insulating film 6 so that the contact holes 7-1 and 7-2 are filled with tungsten, and then etching back tungsten.
Then, wirings 10-1 and 10-2 are formed on the interlayer insulating film 6. The wirings 10-1 has a multi-layered structure comprised of a titanium nitride film 9-1, an Al--Si--Cu alloy film 9-2, and a titanium nitride film 9-3. The wiring layer 10-2 has the same structure as that of the wiring 10-1. The multi-layered structure including an aluminum alloy film sandwiched between titanium nitride films ensures an enhanced electro-migration resistance, which is quite useful as the integration is enhanced. As an alternative, the wirings 10-1 and 10-2 may be made of a single layer film composed of Al--Si--Cu alloy.
As illustrated in FIG. 1, the wiring 10-2 is in most cases designed to have a partially increased width where the wiring 10-2 makes contact with the tungsten plug 8-2. This is because an upper surface of the tungsten plug 8-2 is entirely covered with the wiring 10-2.
However, the above-mentioned structure where an upper surface of the tungsten plug 8-2 is entirely covered with the wiring 10-2 would be a hindrance to enhancement in integration. To solve this problem, there has been suggested a so-called borderless via-hole illustrated in FIG. 2. In accordance with the borderless via-hole structure, a wiring 10A-2 is designed to have a width equal to or smaller than a diameter of the tungsten plug 8-2 even where the wiring 10A-2 makes contact with the tungsten plug 8-2. Hence, the wiring 10A-2 partially covers an upper surface of the tungsten plug 8-2.
The borderless via-hole structure provides a merit that when pattering is carried out for forming the wiring 10A-2 by means of etching which is capable of providing a greater selection ratio relative to tungsten, even if the wiring 10A-2 is not full alignment with the tungsten plug 8-2, it would be possible to avoid that the tungsten plug 8-2 is partially etched, though it would be impossible to decrease a contact area between the wiring 10A-2 and the tungsten plug 8-2.
There has been suggested a semiconductor device having a plurality of wiring layers, which utilizes the above-mentioned borderless via-hole structure and is suitable for higher integration. FIGS. 3A to 3C illustrate respective steps of fabricating such a semiconductor device.
There are formed a MOS transistor, an interlayer insulating film 6, contact holes 7-1 and 7-2, contact plugs 8-1 and 8-2, and lower wirings 10A-1 and 10A-2 each comprised of three films 9-1, 9-2 and 9-3 on a p-type silicon substrate 1 in the same manner as that of the semiconductor device having been explained with reference to FIG. 2. Then, as illustrated in FIG. 3A, a second interlayer insulating film 11 is deposited on a resultant. Then, there is formed a contact hole 12 in the interlayer insulating film 11 reaching the lower wiring 10A-2. The contact hole 12 has a diameter almost equal to a width of the lower wiring 10A-2. As illustrated, the hole 12 includes a first portion 12a terminating at an upper surface of the layer 9-3 of the lower wiring 10A-2 and a second portion 12b passing the layer 9-3 but not reaching a bottom of the layer 9-1.
Then, as illustrated in FIG. 3B, there is formed a tungsten plug 13 which fills the contact hole 12 therewith. Then, as illustrated in FIG. 3C, an upper wiring 15 is formed on the second interlayer insulating film 11. The upper wiring 15 has a three-layered structure including a titanium nitride film 14-1, an Al--Si--Cu alloy film 14-2, and a titanium nitride film 14-3.
The dimensional relationship between the contact hole 12 and the lower wiring 10A-2 is the same as the dimensional relationship between the wiring 10A-2 and the tungsten plug 8-2, but is opposite with respect to top and bottom. That is, the borderless via-hole structure is applied to the connection between the lower and upper wirings 10A-2 and 15 in the semiconductor device illustrated in FIGS. 3A to 3C. Thus, the illustrated semiconductor device could have smaller-sized elements and enhanced electro-migration resistance.
In the illustrated semiconductor device, it would be necessary for surely forming the contact hole 12 that the etching for forming the contact hole 12 is continued after an upper surface of the titanium nitride film 9-3 has appeared. Namely, the contact hole 12 needs to be over-etched. Since misregistration in patterning in photolithography between the contact hole 12 and the wiring 10A-2 is unavoidable, a sidewall of the Al--Si--Cu alloy film 9-2 of the wiring 10A-2 cannot avoid to be exposed to the second portion 12b of the contact hole 12.
If the tungsten plug 13 were formed with the sidewall of the Al--Si--Cu alloy film 9-2 being exposed to the second portion 12b of the contact hole 12, WF.sub.6 gas used as a source gas in CVD reacts with aluminum contained in the Al--Si--Cu alloy film 9-2 to thereby produce insulating material. Accordingly, there is posed a problem that the wiring 10A-2 is eroded with the result of an increase in a wiring resistance and reduction in reliability.